With the proliferation of integrated circuits implemented in the most advanced process technologies, there is a growing need to jointly analyze the effect of multiple sources of failures including variability and aging and to understand, early in the design cycle, their impact on system reliability. Today, conservative margins are required to ensure that devices operate correctly over their full lifetime, despite the impact of aging effects (BTI, HCI) and failure mechanisms such as EM. New methodologies for improved cross-layer modeling and mitigation, if planned early in the design of a product, have the potential to remove unnecessary conservatism, reduce power and cost and improve yield. This workshop is focused on sharing new research on techniques and methodologies for modeling the effects of failures due to transistor aging, variability and other mechanisms all the way from the cell level to system level. New approaches to perform early estimations of system reliability are much needed to enabling reliable, optimized and low-power designs.
The organizers would like to thank all participants and speakers that made the workshop a interesting and successful event. The presentations and the discussion was interesting and stimulating.
Slides of the presentations
Slides of the presentations will be available soon on this website.