Reliability and Variability in CMOS Devices

As FET devices scale toward ~10 nm gate lengths, the discreteness of matter and the particular arrangement of individual atoms in each device result in increased time-zero variability. Moreover, degradation mechanisms, such as TDDB and BTI, can be traced to as-fabricated and generated defects in the gate oxide. Since literally only a handful of defects will be present in each deeply scaled device, while the behavior of these defects is typically stochastic, voltage and temperature dependent, and widely distributed in time, each device will be behaving differently during operation, resulting in additional, time-dependent variability. We will argue that reliability and time-dependent variability of future deeply scaled devices can be understood from the perspective of individual defects. We will discuss the basic physical properties of individual defects. Finally, we will show how these properties can be described statistically, combined with actual workloads and propagated to higher design abstraction levels to project device and circuit lifetime distributions.

About the Speaker

KaczerBen Kaczer is a Principal Scientist at imec, Belgium.  He received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively.   In 1998 he joined the reliability group of imec.  He has co-authored more than 350 journal and conference papers and 2 patents, presented a number of invited papers and tutorials, and received 5 IEEE IRPS Best and Outstanding Paper Awards, 2 IEEE IPFA Best Paper Awards, and the 2011 IEEE EDS Paul Rappaport Award. He has served or is serving at various functions at the IEDM, IRPS, SISC, INFOS, and WoDiM conferences.  He is currently serving on the IEEE T. Electron Dev. Editorial Board.

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