The Resilience Wall: Cross-Layer Solutions

Resilience to hardware failures is essential for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this major challenge, we advocate and examine a cross-layer resilience approach. Two major components of this approach are: 1. System- and software-level effects of circuit-level faults are considered from early stages of system design; and, 2. resilience techniques are implemented across multiple layers of the system stack – from circuit and architecture levels to runtime and applications – such that they work together to achieve required degrees of resilience in a highly energy-efficient manner. Illustrative examples to demonstrate key aspects of cross-layer resilience will be discussed.
Professor Subhasish Mitra
Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel.
Prof. Mitra’s research interests include robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications.  His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. His work on carbon nanotubes, jointly with his students and collaborators, resulted in the demonstration of the first carbon nanotube computer, and it was featured on the cover of NATURE. The NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as “an important, scientific breakthrough” by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.
Prof. Mitra’s honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, “a test of time honor” for an outstanding technical contribution, the Semiconductor Research Corporation’s Technical Excellence Award, and the Intel Achievement Award, Intel’s highest corporate honor.  He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology.
Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on DARPA’s Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

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