Aging on RT Level – Analysis and Monitoring


Traditionally, aging of ICs was investigated by reliability departments and resulted in an overall guardband factor which needed to be considered during IC design. This approach is increasingly less appropriate. Transistor-level aging models, however, are not suitable for analyzing large circuits. Therefore, gate level timing models incorporating aging have been developed. We will show aging information can be abstracted further from gate to RT level – without loss of accuracy. We will also discuss how such RT level timing models can be employed to monitor the aging of digital circuits during their operation.

About the Speaker

Ulf Schlichtmann spent about 10 years in the semiconductor industry (Siemens, Infineon), in various engineering, management and executive positions. Among other assignments, he was responsible for Infineon’s design libraries worldwide, managing about 125 engineers in Munich, Sophia Antipolis, San Jose and Singapore. In 2003, he joined TUM as head of the Institute for Electronic Design Automation. From 2007-2013 he served as Dean and Vice Dean of TUM’s Department of Electrical and Computer Engineering.
His research focuses on algorithms for the efficient design of electronic circuits and systems. Abstraction levels from the transistor up to the system level are addressed. In recent years, he has put emphasis especially on the analysis and optimization of circuits and systems for reliability and resilience, with cross-layer techniques increasingly gaining in importance.

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