Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems – March 18th 2016 – Dresden, Germany
Summary Recent years, to enhance automotive functionalities for more driving enjoyment and hazard prevention, more and more electronic devices are used to monitor and control automotive operation. To ensure the safety of drivers and passengers, these electronic devices need higher Continue reading Reliability and Safety Challenges of Automotive Devices
Traditionally, aging of ICs was investigated by reliability departments and resulted in an overall guardband factor which needed to be considered during IC design. This approach is increasingly less appropriate. Transistor-level aging models, however, are not suitable for analyzing large Continue reading Aging on RT Level – Analysis and Monitoring
Robert C. Aitken is an ARM Fellow and technology lead for ARM Research. His areas of responsibility include technology roadmapping, library architecture for advanced process nodes, and low power design. His research interests include design for variability, resilient computing, and Continue reading Accuracy versus Breadth in Cross-Layer Solutions
As FET devices scale toward ~10 nm gate lengths, the discreteness of matter and the particular arrangement of individual atoms in each device result in increased time-zero variability. Moreover, degradation mechanisms, such as TDDB and BTI, can be traced to Continue reading Reliability and Variability in CMOS Devices
Overview In the analog circuit design domain Spice simulators are the most commonly used tools for design exploration and verification. Consequentially an integration of add-on models for aging effects like BTI and HCI using one of several available interfaces is Continue reading Aging Models for Analog Circuit Level Simulations – Integration and Deployment Challenges
In this talk, Yongsheng Sun(孙 永生), will introduce HiSilicon (海思) and describe their cutting edge products. HiSilicon is one of the largest fabless companies and currently ships chips in the most advanced process technologies. Due to their success and huge number of products Continue reading Reliability Challenges for Large ASICs
Summary Resilience to hardware failures is essential for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this major challenge, we advocate and examine a cross-layer resilience Continue reading The Resilience Wall: Cross-Layer Solutions