The proceedings of the workshop are available through Open Proceedings at this link : http://ceur-ws.org/Vol-1566
The workshop program can be downloaded : ERMAVSS_Program.
Invited Talks
Reliability and Variability in CMOS Devices
As FET devices scale toward ~10 nm gate lengths, the discreteness of matter and the particular arrangement of individual atoms in each device result in increased time-zero variability. Moreover, degradation mechanisms, such as TDDB and BTI, can be traced to as-fabricated and generated defects in the gate oxide. Since literally only a handful of defects will be present in each deeply scaled device, while the behavior of these defects is typically stochastic, voltage and temperature dependent, and widely distributed in time, each device will be behaving differently during operation, resulting in additional, time-dependent variability. We will argue that reliability and ...
Accuracy versus Breadth in Cross-Layer Solutions
Robert C. Aitken is an ARM Fellow and technology lead for ARM Research. His areas of responsibility include technology roadmapping, library architecture for advanced process nodes, and low power design. His research interests include design for variability, resilient computing, and memory robustness. His group has participated in numerous chip tape-outs, including 8 at or below the 16nm node. He has published over 70 technical papers, on a wide range of topics. Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He has given tutorials and ...
The Resilience Wall: Cross-Layer Solutions
Summary Resilience to hardware failures is essential for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this major challenge, we advocate and examine a cross-layer resilience approach. Two major components of this approach are: 1. System- and software-level effects of circuit-level faults are considered from early stages of system design; and, 2. resilience techniques are implemented across multiple layers of the system stack – from circuit and architecture levels to runtime and applications – such that they work together to achieve required degrees of resilience in a ...
Aging on RT Level – Analysis and Monitoring
Traditionally, aging of ICs was investigated by reliability departments and resulted in an overall guardband factor which needed to be considered during IC design. This approach is increasingly less appropriate. Transistor-level aging models, however, are not suitable for analyzing large circuits. Therefore, gate level timing models incorporating aging have been developed. We will show aging information can be abstracted further from gate to RT level – without loss of accuracy. We will also discuss how such RT level timing models can be employed to monitor the aging of digital circuits during their operation. About the Speaker Ulf Schlichtmann spent about 10 years ...