The proceedings of the workshop are available through Open Proceedings at this link :


The workshop program can be downloaded : ERMAVSS_Program.


Invited Talks

Reliability Challenges for Large ASICs

In this talk, Yongsheng Sun(孙 永生), will introduce HiSilicon (海思) and describe their cutting edge products. HiSilicon is one of the largest fabless companies and currently ships chips in the most advanced process technologies. Due to their success and huge number of products being shipped, reliability is a top concern. Sarinda Wang will describe the key challenges when designing highly reliable, silicon intenstive products. Specific issues will also be discussed to sensitisize the audience to the real-world reliability problems faced when shipping products in the most advanced technologies. About the Speaker Yongsheng Sun received the B.S and M.S degree in Microelectronics from the University of Electronic ...

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Aging Models for Analog Circuit Level Simulations – Integration and Deployment Challenges

Overview In the analog circuit design domain Spice simulators are the most commonly used tools for design exploration and verification. Consequentially an integration of add-on models for aging effects like BTI and HCI using one of several available interfaces is considered a straightforward enhancement allowing to address reliability analysis and verification. This talk will give an outline of all the not-so-straightforward challenges arising from the integration and deployment of complex aging models in the harsh environmental conditions of state-of-the-art EDA tool ecosystems. About the Speaker Peter Rotter was born in Germany in 1965. He received the diploma degree in physics from the University of Regensburg ...

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The Resilience Wall: Cross-Layer Solutions

Summary Resilience to hardware failures is essential for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this major challenge, we advocate and examine a cross-layer resilience approach. Two major components of this approach are: 1. System- and software-level effects of circuit-level faults are considered from early stages of system design; and, 2. resilience techniques are implemented across multiple layers of the system stack – from circuit and architecture levels to runtime and applications – such that they work together to achieve required degrees of resilience in a ...

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Aging on RT Level – Analysis and Monitoring

Traditionally, aging of ICs was investigated by reliability departments and resulted in an overall guardband factor which needed to be considered during IC design. This approach is increasingly less appropriate. Transistor-level aging models, however, are not suitable for analyzing large circuits. Therefore, gate level timing models incorporating aging have been developed. We will show aging information can be abstracted further from gate to RT level – without loss of accuracy. We will also discuss how such RT level timing models can be employed to monitor the aging of digital circuits during their operation. About the Speaker Ulf Schlichtmann spent about 10 years ...

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Reliability and Variability in CMOS Devices

As FET devices scale toward ~10 nm gate lengths, the discreteness of matter and the particular arrangement of individual atoms in each device result in increased time-zero variability. Moreover, degradation mechanisms, such as TDDB and BTI, can be traced to as-fabricated and generated defects in the gate oxide. Since literally only a handful of defects will be present in each deeply scaled device, while the behavior of these defects is typically stochastic, voltage and temperature dependent, and widely distributed in time, each device will be behaving differently during operation, resulting in additional, time-dependent variability. We will argue that reliability and ...

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