The proceedings of the workshop are available through Open Proceedings at this link :


The workshop program can be downloaded : ERMAVSS_Program.


Invited Talks

Reliability and Variability in CMOS Devices

As FET devices scale toward ~10 nm gate lengths, the discreteness of matter and the particular arrangement of individual atoms in each device result in increased time-zero variability. Moreover, degradation mechanisms, such as TDDB and BTI, can be traced to as-fabricated and generated defects in the gate oxide. Since literally only a handful of defects will be present in each deeply scaled device, while the behavior of these defects is typically stochastic, voltage and temperature dependent, and widely distributed in time, each device will be behaving differently during operation, resulting in additional, time-dependent variability. We will argue that reliability and ...

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Reliability and Safety Challenges of Automotive Devices

Summary Recent years, to enhance automotive functionalities for more driving enjoyment and hazard prevention, more and more electronic devices are used to monitor and control automotive operation. To ensure the safety of drivers and passengers, these electronic devices need higher reliability. In this talk, we will present what Mentor Graphics are doing to prepare for these reliability and safety challenges in pre-silicon, post-silicon and system operations.   About the Speaker Wu-Tung Cheng is a Chief Scientist and Advanced Test Research Director in Mentor Graphics. He is an IEEE fellow since year 2000. He has over 150 publications and 50 patents in semiconductor manufacture test and diagnosis area. In 2006, ...

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Aging on RT Level – Analysis and Monitoring

Traditionally, aging of ICs was investigated by reliability departments and resulted in an overall guardband factor which needed to be considered during IC design. This approach is increasingly less appropriate. Transistor-level aging models, however, are not suitable for analyzing large circuits. Therefore, gate level timing models incorporating aging have been developed. We will show aging information can be abstracted further from gate to RT level – without loss of accuracy. We will also discuss how such RT level timing models can be employed to monitor the aging of digital circuits during their operation. About the Speaker Ulf Schlichtmann spent about 10 years ...

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Accuracy versus Breadth in Cross-Layer Solutions

Robert C. Aitken is an ARM Fellow and technology lead for ARM Research. His areas of responsibility include technology roadmapping, library architecture for advanced process nodes, and low power design. His research interests include design for variability, resilient computing, and memory robustness. His group has participated in numerous chip tape-outs, including 8 at or below the 16nm node. He has published over 70 technical papers, on a wide range of topics.  Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP.  He has given tutorials and ...

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Aging Models for Analog Circuit Level Simulations – Integration and Deployment Challenges

Overview In the analog circuit design domain Spice simulators are the most commonly used tools for design exploration and verification. Consequentially an integration of add-on models for aging effects like BTI and HCI using one of several available interfaces is considered a straightforward enhancement allowing to address reliability analysis and verification. This talk will give an outline of all the not-so-straightforward challenges arising from the integration and deployment of complex aging models in the harsh environmental conditions of state-of-the-art EDA tool ecosystems. About the Speaker Peter Rotter was born in Germany in 1965. He received the diploma degree in physics from the University of Regensburg ...

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